Common Gate Amplifier Easy Calculation

Contents

Common gate amplifier is the basic single stage FET along with common drain and common source FET. This configuration is mainly used as a voltage amplifier or current buffer.

This configuration uses source as the input, drain as the output, and gate is grounded or “common”. This is why it is called a common gate amplifier. For a transistor, it is equal to the common base amplifier.

A common gate amplifier is mainly used for CMOS RF receivers because of its property of impedance matching and has lower noise. Nonetheless, this configuration is the least used amplifier than the common source amplifier.

When analyzing a transistor, we will analyze it with and without the output resistance of the transistor (ro).

Common Gate Amplifier Without Output Resistance (ro)

Observe the common gate amplifier circuit below.

When using a common gate FET, we connect the gate to the ground, the drain with drain resistance and VDD, and source with Vin.

Our objective is finding the value of:

• Voltage gain (AV)
• Input resistance (Rin)
• Output resistance (Rout)

How do we calculate those three? We can use the small signal model equivalent to our circuit above.

First, the basic small signal model of the transistor is

From the circuit we can tell that:

• Gate is connected to the ground
• Drain is connected to the drain resistance (RD), Vout, and VDD
• Source is connected to the Vin

Keep in mind the VDD value doesn’t change at any time, so we draw it as a ground.

Thus our small signal model will be:

The voltage gain will be as usual

Don’t forget that we still have Vgs in the circuit.

Since the current from the drain side is flowing from the VDD, thus

The output voltage (Vout) is equal to

Where

Then we rewrite Vout into

So what is the value of Vgs? The Vgs is simply

Since Vg is connected to ground, then Vg = 0 while Vs is connected to Vin.

Looking back to our Vout equation, we write

Our next objective is to find the input resistance Rin. We draw the small signal model once more below but replace the Vin with Vtest for testing this time. It won’t be different.

The input resistance is

This will be easy to finish because we have a dependent current source in the middle of drain and source. Since a current in series connection is equal then

Where the direction of the dependent current source is the opposite of our itest.

The Vgs is

Thus, our itest value is

Hence,

The value of gm is independent from RD.

Our last objective is to find the output resistance (Rout). But first, we have to draw the small signal model. Because we want to calculate something on the output side, we connect our Vtest to the output test (drain).

Our voltage source Vin will be replaced by a short circuit since we need to turn off every independent source when analyzing output resistance.

The Rout is

Now we assign the current direction for easier understanding with KCL on the drain.

And the itest is

The Vgs value is

Thus,

The final small signal model for our common gate amplifier is

Common Gate Amplifier With Output Resistance (ro)

First observe a common gate amplifier below,

And we draw the small signal model

The VDD is replaced by ground just the same as the previous example above (common gate amplifier without ro).

Our objective is to find the values of:

• Voltage gain (AV)
• Input resistance (Rin)
• Output resistance (Rout)

First we will calculate the output resistance (Rout). We will turn off the Vin as it is an independent source then connect the voltage source Vtest which generates itest.

Applying the KCL to the upper side,

Resulting in

Since Vgs = Vg – Vs = 0 – 0 = 0, then

Next is to calculate input resistance.

We apply KCL to the node below the dependent current source and mark it with Node 1.

The current itest must be equal to the gmVgs and current flowing to ro.

We apply KCL again on top of the ro and mark it with Node 2. It is difficult to determine the direction of the node currents so we will assume all the currents are leaving the node.

The node currents are

The Vgs is

Substitute Vgs to the Node 1 equation results in

And substitute Vgs into Node 2 equation

We will use elimination to our last two equations

Skipping the difficult calculation, we get

Assume that ro is very large (infinite) then we can ignore the RD and 1. Hence,

Now our last objective is to calculate the voltage gain. We can do this easily by replacing the Vtest with the Vin as the original circuit.

We just rename Vtest with Vin in the Vout equation above

To make it simpler, we will multiply it with ro/ro

We divide all the sides with Vin to get AV

Assume that ro is very large (infinite) then we can ignore the 1 from top and bottom side. Hence,