Common Gate Amplifier Easy Calculation

Common gate amplifier is the basic single stage FET along with common drain and common source FET. This configuration is mainly used as a voltage amplifier or current buffer.

This configuration uses source as the input, drain as the output, and gate is grounded or “common”. This is why it is called a common gate amplifier. For a transistor, it is equal to the common base amplifier.

A common gate amplifier is mainly used for CMOS RF receivers because of its property of impedance matching and has lower noise. Nonetheless, this configuration is the least used amplifier than the common source amplifier.

When analyzing a transistor, we will analyze it with and without the output resistance of the transistor (r_o).

Common Gate Amplifier Without Output Resistance (ro)

Observe the common gate amplifier circuit below.

When using a common gate FET, we connect the gate to the ground, the drain with drain resistance and V_DD, and source with Vin.

Our objective is finding the value of:

• Voltage gain (A_V)
• Input resistance (R_in)
• Output resistance (R_out)

How do we calculate those three? We can use the small signal model equivalent to our circuit above.

First, the basic small signal model of the transistor is

From the circuit we can tell that:

• Gate is connected to the ground
• Drain is connected to the drain resistance (R_D), V_out, and V_DD
• Source is connected to the V_in

Keep in mind the V_DD value doesn’t change at any time, so we draw it as a ground.

Thus our small signal model will be:

The voltage gain will be as usual

Don’t forget that we still have V_gs in the circuit.

Since the current from the drain side is flowing from the V_DD, thus

The output voltage (V_out) is equal to

Where

Then we rewrite V_out into

So what is the value of V_gs? The V_gs is simply

Since V_g is connected to ground, then V_g = 0 while V_s is connected to V_in.

Looking back to our V_out equation, we write

Our next objective is to find the input resistance R_in. We draw the small signal model once more below but replace the V_in with V_test for testing this time. It won’t be different.

The input resistance is

This will be easy to finish because we have a dependent current source in the middle of drain and source. Since a current in series connection is equal then

Where the direction of the dependent current source is the opposite of our itest.

The V_gs is

Thus, our i_test value is

Hence,

The value of g_m is independent from R_D.

Our last objective is to find the output resistance (R_out). But first, we have to draw the small signal model. Because we want to calculate something on the output side, we connect our V_test to the output test (drain).

Our voltage source V_in will be replaced by a short circuit since we need to turn off every independent source when analyzing output resistance.

The R_out is

Now we assign the current direction for easier understanding with KCL on the drain.

And the i_test is

The V_gs value is

Thus,

The final small signal model for our common gate amplifier is

Common Gate Amplifier With Output Resistance (ro)

First observe a common gate amplifier below,

And we draw the small signal model

The V_DD is replaced by ground just the same as the previous example above (common gate amplifier without r_o).

Our objective is to find the values of:

• Voltage gain (A_V)
• Input resistance (R_in)
• Output resistance (R_out)

First we will calculate the output resistance (R_out). We will turn off the V_in as it is an independent source then connect the voltage source V_test which generates i_test.

Applying the KCL to the upper side,

Resulting in

Since V_gs = V_g – V_s = 0 – 0 = 0, then

Next is to calculate input resistance.

We apply KCL to the node below the dependent current source and mark it with Node 1.

The current itest must be equal to the g_mV_gs and current flowing to r_o.

We apply KCL again on top of the r_o and mark it with Node 2. It is difficult to determine the direction of the node currents so we will assume all the currents are leaving the node.

The node currents are

The V_gs is

Substitute V_gs to the Node 1 equation results in

And substitute V_gs into Node 2 equation

We will use elimination to our last two equations

Skipping the difficult calculation, we get

Assume that r_o is very large (infinite) then we can ignore the R_D and 1. Hence,

Now our last objective is to calculate the voltage gain. We can do this easily by replacing the V_test with the V_in as the original circuit.

We just rename V_test with V_in in the Vout equation above

To make it simpler, we will multiply it with r_o/r_o

We divide all the sides with V_in to get A_V

Assume that r_o is very large (infinite) then we can ignore the 1 from top and bottom side. Hence,

Frequently Asked Questions