The JK flip flop excitation table is very useful to remember how a JK flip flop works rather than remembering a bunch of logic gates inside it to grasp how we can control its output.
JK flip flop is made to eliminate the weakness of the SR flip flop that has uncertain output when both inputs for S and R are 1. Just as its purpose, a JK flip flop also has two inputs with functions of set, reset, hold, and toggle.
Excitation Table for JK Flip Flops
The JK flip flop will toggle its output when both input J and K are 1, unlike the SR flip flop where its output is uncertain.
Observe the positive-edge JK flip flop symbol below where we will have:
- J and K inputs
- Q and Q’ outputs
- Clock (CLK)
Keep in mind that the positive-edge JK flip flop only responds to rising edge of the clock (CLK).
And the positive-edge JK flip flop excitation table, or JK flip flop truth table below.
From the perspective of Q (output) we can list its changes of output when the CLK (clock) is rising, they are:
- J = 0 and K = 0, then the output remains the same (HOLD)
- J = 0 and K = 1, then the output is 0 (RESET)
- J = 1 and K = 0, then the output is 1 (SET)
- J = 1 and K = 1, then the output is inverted (TOGGLE)
So what if the CLK is staying low (not rising)?
Then the state of Q will remain the same since the output can be changed when the CLK is rising.
The more detailed JK Flip Flop excitation table can be seen below.
After learning about the positive-edge JK flip flop, we will learn about the negative-edge JK flip flop. Those two are not different, only the negative-edge means the JK flip flop only responds to the falling edge of the clock (CLK).
Below is the negative-edge JK flip flop symbol.
And the negative-edge JK flip flop excitation table, or JK flip flop truth table below.
JK Flip Flop Circuit Diagram
Just like we stated above, the JK flip flop comes to eliminate SR flip flop. This means the SR flip is modified a little to fulfill our need. The circuit diagram of the JK flip flop can be seen below:
As we can see above, we still have the SR flip flop but its inputs are connected to AND gates where we insert our inputs.
To understand its operation fully, observe the important points below:
- The R input is tied to the output of J output
- The S input is tied to the output of K output
- The R output (Qn) is sent to K input as its feedback
- The S output (Qn’) is sent to J input as its feedback
- CLK is connected to the CT (Clock Transition) circuit
- CT circuit produces narrow edge pulse at every clock transition
JK Flip Flop Excitation Table
After learning its circuit diagram, logic gates, and operation, now we will move on to the JK flip flop excitation table. In the table below we have:
- J and K = inputs
- Qn = present output
- Qn+1 = final output
Assume that table below is when the rising edge occurred.
The truth table above is equivalent to the Karnaugh map below.
The Karnaugh Map equation for the JK flip flop excitation table is expressed below:
JK Flip Flop Timing Diagram
After learning about the JK flip flop circuit diagram and truth table, we will now learn them with its clock pulse included. The clock pulse is a positive edge pulse or rising edge pulse. The output will only change when the rising edge is detected no matter how long it is ON or OFF.
CLK = 1 means the rising edge is detected. The output will be Q and Q’.
The operation sequence of the timing diagram above is summarized below:
- First, J = 0, K = 1, CLK = 1, then Q = 0 and Q’ = 1.
- Second, J = 1, K = 0, CLK = 1, then Q = 1 and Q’ = 0.
- Third, J = 1, K = 1, CLK = 1, then Q = 0 and Q’ = 1.
- Fourth, J = 0, K = 0, CLK = 1, then Q = 0 and Q’ = 1.
Remember that the third sequence will toggle the present output (Q = 1 from the second sequence) to the final output Q = 0.
The last sequence will not change the output from the third sequence.
